Publications
Click a title to open the paper at the publisher (DOI) or the author copy. Where available, buttons link to the code, datasets and trained models behind each paper. Search by title, author, venue or year, or filter by type.
2026
Conference
WALET: SHAP-Guided Classification of Wafer-Level E-Test Variability for Early Manufacturing Risk Detection
IEEE 44th VLSI Test Symposium (VTS)
·
2026
Conference
Covert Information Leakage Via Hardware-Induced Spectral Shaping
IEEE International Symposium on Hardware Oriented Security and Trust
·
2026
2025
Journal
Battery safety and security for electric urban air mobility
Cell Reports Physical Science
·
2025
Journal
Biosecurity Primitive: Polymerase X‐based Genetic Physical Unclonable Functions
Advanced Science
·
2025
Conference
An SMT-Based Method for Identifying State-Holding Elements in Extracted Netlists
IEEE International Test Conference (ITC)
·
2025
Conference
Teaching Llamas to Test: A Language-Based Approach
IEEE International Test Conference (ITC)
·
2025
Conference
Unveiling the Mask: Trusted Semiconductor Manufacturing through Wafer-Level Mask-Set Attestation
IEEE/ACM International Conference On Computer Aided Design (ICCAD)
·
2025
Conference
Experimental Characterization and Empirical Beam Steering Analysis of a 28 GHz 1-Bit 8x8 RIS Reflectarray via Conductivity Pattern Modulation
International Symposium on Wireless Personal Multimedia Communications (WPMC)
·
2025
Conference
The Pulse-Shaping Trojan: Refinements and New Results
61st Allerton Conference on Communication, Control, and Computing
·
2025
Journal
A TRAP for SAT: On the Imperviousness of a Transistor-Level Programmable Fabric to Satisfiability-Based Attacks
IACR Transactions on Cryptographic Hardware and Embedded Systems (T.CHES)
·
2025
Journal
Modeling Bidirectional Switches for Enabling Logic Equivalence Checking in a Transistor-Level Programmable Fabric
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T. CAD)
·
2025
Journal
Physically Secure Logic Locking With Nanomagnet Logic
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T. CAD)
·
2025
Conference
Can Llamas Learn the Language of Test?
Proceedings of the SRC Technology and Talent for the 21st Century Conference (TECHCON)
·
2025
Conference
FREEDOM: FPGA-based Hardware Redaction Emulator
Proceedings of the International Symposium on Field-Programmable Custom Computing Machines (FCCM 2025)
·
2025
Conference
Efficient and Secure Cloud-based Split Logic Synthesis
Proceedings of the IEEE Dallas Circuit and System Conference (DCAS)
·
2025
Conference
Enhancing Metrology to E-test Correlation Model Accuracy through Process Expertise Integration
Proceedings of the IEEE VLSI Test Symposium (VTS)
·
2025
Conference
FPGA-based Hardware Redaction Bitstream Fuzzing Attack
Proceedings of the IEEE Asian-Pacific Design Automation Conference (ASP-DAC)
·
2025
Book chapter
Design Obfuscation and Performance Locking Solutions for Mixed-Signal, Analog and RF ICs
In R. Vemuri and J. Emmert (Editors), Advanced in hardware Design for Security and Trust, CRC Press
·
2025
Book chapter
Security Verification for Next-generation SoCs
In R. Vemuri and J. Emmert (Editors), Advanced in hardware Design for Security and Trust, CRC Press
·
2025
2024
Journal
The History, Landscape, and Outlook of Human Cell Line Authentication and Security
SLAS Discovery
·
2024
Journal
Bit-by-Bit: Investigating the Vulnerabilities of Binary Neural Networks to Adversarial Bit Flipping
Transactions on Machine Learning Research
·
2024
Conference
Generation and Evaluation of Synthetic Process Control Monitoring Data
Proceedings of the IEEE International Test Conference (ITC)
·
2024
Conference
NSPG: Natural language Processing-based Security Property Generator for Hardware Security Assurance
Proceedings of the ACM/IEEE Design Automation Conference
·
2024
Conference
19-GHz VCO with Phase Noise of-117 dBc/Hz at 1-MHz Offset Using an Array of Near Minimum Size Transistors and Intelligent Post Fabrication Selection
Proceedings of the IEEE/MTT-S International Microwave Symposium (IMS)
·
2024
Conference
Testing a Transistor-Level Programmable Fabric: Challenges and Solutions
Proceedings of the IEEE VLSI Test Symposium (VTS)
·
2024
Conference
On the Sensitivity of Analog Artificial Neural Network Models to Process Variation
Proceedings of the IEEE VLSI Test Symposium (VTS)
·
2024
2023
Journal
Statistical Methods for Detecting Recycled Electronics: From ICs to PCBs and Beyond
IEEE Design & Test of Computers
·
2023
Conference
Machine Learning-Based Adaptive Outlier Detection For Underkill Reduction In Analog/RF IC Testing
Proceedings of the IEEE VLSI Test Symposium (VTS)
·
2023
Conference
MANTIS: Machine Learning-Based Approximate Modeling of Redacted Integrated Circuits
Proceedings of the IEEE Design Automation and Test in Europe (DATE)
·
2023
Conference
Quo Vadis Signal? Automated Directionality extraction for Post-Programming Verification of a Transistor-Level Programmable Fabric
Proceedings of the IEEE Design Automation and Test in Europe (DATE)
·
2023
2022
Journal
Phase Noise Reduction in LC VCO’s Using an Array of Cross-Coupled Nanoscale MOSFETs and Intelligent Post-Fabrication Selection
IEEE Transactions on Microwave Theory and Techniques
·
2022
Journal
Physically and Algorithmically Secure Logic Locking with Hybrid CMOS-Nanomagnet Logic
Bulletin of the American Physical Society
·
2022
Conference
Efficient CNN-Based Super Resolution Algorithms for mmWave Mobile Radar Imaging
Proceedings of the IEEE International Conference on Image Processing (ICIP)
·
2022
Conference
Reducing Underkill Using Unsupervised Machine Learning-Based Method in Analog/RF IC Testing
Proceedings of the SRC Technology and Talent for the 21st Century Conference (TECHCON)
·
2022
Conference
A Defect Tolerance Framework for Improving Yield
Proceedings of the ACM/IEEE Design Automation Conference
·
2022
Conference
Physically and Algorithmically Secure Logic Locking with Hybrid CMOS/Nanomagnet Logic Circuits
Proceedings of the IEEE Design, Automation & Test in Europe Conference (DATE)
·
2022
Conference
Machine Learning-Based Overkill Reduction through Inter-Test Correlation
Proceedings of the IEEE VLSI Test Symposium (VTS)
·
2022
Conference
MTBoM: Metal Trace to Bill of Materials Generation for PCB Reverse Engineering
Proceedings of the IEEE Dallas Circuit and System Conference (DCAS)
·
2022
Conference
Toward Accurate Timing Analysis for Transistor-Level Programmable Fabrics
Proceedings of the IEEE Dallas Circuit and System Conference (DCAS)
·
2022
Best Paper Award
Conference
Investigating the Effect of different eFPGAs fabrics on Logic Locking through HW Redaction
Proceedings of the IEEE Dallas Circuit and System Conference (DCAS)
·
2022
Book chapter
Hardware-Induced Covert Channels in Wireless Networks: Risks and Remedies
In S. Jajodia, R. Samarati and M. Yung (Editors), Encyclopedia of Cryptography, Security and Privacy, Springer
·
2022
Patent
Field Programmable Transistor Arrays
Patent US 11,362,362 (continuation) · Issued Jun. 28, 2022
·
2022
Patent
Methods for Generating Integrated Circuit (IC) Layout Synthetic Patterns and Related Computer Program Products
Patent US 11,449,658 · Issued Sep. 20, 2022
·
2022
2021
Journal
TPE: A Hardware-Based TLB Profiling Expert for Workload Reconstruction
IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)
·
2021
Journal
Proof-Carrying Hardware-Based Information Flow Tracking in Analog/Mixed-Signal Designs
IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS)
·
2021
Journal
On Improving Hotspot Detection Through Synthetic Pattern-Based Database Enhancement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T.CAD)
·
2021
Journal
Bias Busters: Robustifying DL-based Lithographic Hotspot Detectors Against Backdooring Attacks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T. CAD)
·
2021
Conference
Machine-Learning Based Overkill Reduction using Correlation within the Probe Tests
Proceedings of the SRC Technology and Talent for the 21st Century Conference (TECHCON)
·
2021
Conference
Secure Logic Locking with Strain-Protected Nanomagnet Logic
Proceedings of the Design Automation Conference (DAC)
·
2021
Conference
Functional Locking through Omission: From HLS to Obfuscated Design
Proceedings of the IEEE International Conference on Computer Design (ICCD)
·
2021
Conference
Trim Time Reduction in Analog/RF ICs Based on Inter-Trim Correlation
Proceedings of the IEEE VLSI Test Symposium (VTS)
·
2021
Best Paper Award Candidate
Patent
Genetic Physical Unclonable Functions and Methods of Use Thereof
Patent PCT/US2021/033108 · Filed May 18, 2021
·
2021
2020
Journal
Hunting Security Bugs in SoC Designs: Lessons Learned
IEEE Design & Test of Computers (D&T)
·
2020
Journal
Amplitude-Modulating Analog/RF Hardware Trojans in Wireless Networks: Risks and Remedies
IEEE Transactions on Information Forensics and Security (T.IFS)
·
2020
Journal
A Hardware-Based Architecture-Neutral Framework for Real-Time IoT Workload Forensics
IEEE Transactions on Computers (T. COMP)
·
2020
Conference
Hardware-Based Detection of Spectre Attacks: A Machine Learning Approach
Proceedings of the EEE Asian Hardware–Oriented Security and Trust Symposium (Asian-HOST)
·
2020
Conference
Defect Tolerance Estimation and Netlist Optimization for Digital Designs
Proceedings of the SRC Technology and Talent for the 21st Century Conference (TECHCON)
·
2020
Conference
CASPER: CAD Framework for a Novel Transistor-Level Programmable Fabric
Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)
·
2020
Conference
DECOY: DEflection-Driven HLS-Based Computation Partitioning for Obfuscating Intellectual PropertY
Proceedings of the ACM Design Automation Conference (DAC)
·
2020
Conference
ATTEST: Application-Agnostic Testing of a Novel Transistor-Level Programmable Fabric
Proceedings of the IEEE VLSI Test Symposium (VTS)
·
2020
Conference
Range Controlled Floating-Gate Transistors: A Unified Solution for Unlocking and Calibrating Analog ICs
Proceedings of the IEEE Design Automation and Test in Europe (DATE)
·
2020
Conference
An Efficient MILP-Based Aging-Aware Floorplanner for Multi-Context Coarse-Grained Runtime Reconfigurable FPGA
Proceedings of the IEEE Design Automation and Test in Europe (DATE)
·
2020
Patent
Field Programmable Transistor Arrays
Patent US 10,855,285 (continuation) · Issued Dec. 1, 2020
·
2020
2019
Journal
CAPE: A Cross-Layer Framework for Accurate Microprocessor Power Estimation
Integration: The VLSI Journal (JVLSI)
·
2019
Journal
Demonstrating and Mitigating the Risk of a FEC-based Hardware Trojan in Wireless Networks
IEEE Transactions on Information Forensics and Security (T.IFS)
·
2019
Conference
Design Space Exploration For Hotspot Detection
Proceedings of the IEEE International Workshop on Microprocessor Test and Verification (MTV)
·
2019
Conference
Extending the Lifetime of Coarse-Grained Runtime Reconfigurable FPGAs by Balancing Processing Element Usage
Proceedings of the International Conference on Field-Programmable Technology (ICFPT)
·
2019
Conference
Revisiting Capacitor-Based Trojan Design and Detection
Proceedings of the IEEE International Conference on Computer Design (ICCD)
·
2019
Conference
VIPER: A Versatile and Intuitive Pattern GenERator for Early Design Space Exploration
Proceedings of the IEEE International Test Conference (ITC)
·
2019
Conference
IPP: Subtle Anomaly Detection of Microscopic Probes using Deep Learning Based Image Completion
Proceedings of the IEEE International Test Conference (ITC)
·
2019
Conference
Machine Learning-Based Hotspot Detection: Fallacies, Pitfalls and Marching Orders
Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD)
·
2019
Conference
Wafer-Level Adaptive Vmin Calibration Seed Forecasting using Inter-Vmin Correlation
Proceedings of the SRC Technology and Talent for the 21st Century Conference (TECHCON)
·
2019
Conference
VIPER: A Versatile and Intuitive Pattern GenERator for Early Design Space Exploration
Proceedings of the SRC Technology and Talent for the 21st Century Conference (TECHCON)
·
2019
Conference
Post-Production Calibration of Analog/RF ICs: Recent Developments and A Fully Integrated Solution
Proceedings of the International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
·
2019
Conference
Trusted and Secure Design of Analog/RF ICs: Recent Developments
Proceedings of the International On-Line Test Symposium (IOLTS)
·
2019
Conference
Automated Die Inking through On-line Machine Learning
Proceedings of the International On-Line Test Symposium (IOLTS)
·
2019
Conference
Functional Obfuscation of Hardware Accelerators through Selective Partial Design Extraction onto an Embedded FPGA
Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)
·
2019
Conference
Machine Learning-based Noise Classification and Decomposition in RF Transceivers
Proceedings of the IEEE VLSI Test Symposium (VTS)
·
2019
Conference
Hardware-based Real-time Workload Forensics via Frame-level TLB Profiling
Proceedings of the IEEE VLSI Test Symposium (VTS)
·
2019
Conference
Analog Performance Locking through Neural Network-Based Biasing
Proceedings of the IEEE VLSI Test Symposium (VTS)
·
2019
Conference
Wafer-Level Adaptive Vmin Calibration Seed Forecasting
Proceedings of the IEEE Design Automation and Test in Europe (DATE)
·
2019
Conference
Design obfuscation with Selective Post-Fabrication Transistor-level Programming
Proceedings of the IEEE Design Automation and Test in Europe (DATE)
·
2019
2018
Conference
Hardware Dithering: A Run-Time Trojan Neutralization Method for Wireless Cryptographic ICs
Proceedings of the IEEE International Test Conference (ITC)
·
2018
Conference
On the Use of Bayesian Networks for Resource-Efficient Self-Calibration of Analog/RF ICs
Proceedings of the IEEE International Test Conference (ITC)
·
2018
Conference
Pattern Matching Rule Ranking Through Design of Experiments and Silicon Validation
Proceedings of the ASM International Symposium for Test and Failure Analysis (ISTFA)
·
2018
Conference
Towards a Cross-Layer Framework for Accurate Power Modeling of Microprocessor Designs
Proceedings of the International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)
·
2018
Conference
Wafer-Level Adaptive Vmin Seed Forecasting
Proceedings of the SRC Technology and Talent for the 21st Century Conference (TECHCON)
·
2018
Conference
Hotspot Detection Through Clustering Based Root Cause Learning
Proceedings of the SRC Technology and Talent for the 21st Century Conference (TECHCON)
·
2018
Top-10 Student Presentations Award
Conference
Enhanced Hotspot Detection Through Synthetic Pattern Generation and Design of Experiments
Proceedings of the IEEE VLSI Test Symposium (VTS)
·
2018
Conference
Hardware-Assisted Rootkit Detection via On-line Statistical Fingerprinting of Process Execution
Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE)
·
2018
Conference
Towards Provably-Secure Performance Locking
Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE)
·
2018
Book chapter
Gaussian Process-Based Wafer-Level Correlation Modeling and its Applications
In A. Elfadel, D. Bonning and X. Li (Editors), Machine Learning in VLSI Computer-Aided Design, Springer
·
2018
2017
Journal
Trusted Analog/Mixed-Signal/RF ICs: A Survey and a Perspective
IEEE Design & Test of Computers (D&T)
·
2017
Journal
Yield Forecasting Across Semiconductor Fabrication Plants and Design Generations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T. CAD)
·
2017
Journal
Data Secrecy Protection through Information Flow Tracking in Proof-Carrying Hardware IP (Part I: Framework Fundamentals)
IEEE Transactions on Information Forensics and Security (T.IFS)
·
2017
Journal
Data Secrecy Protection through Information Flow Tracking in Proof-Carrying Hardware IP (Part II: Framework Automation)
IEEE Transactions on Information Forensics and Security (T.IFS)
·
2017
Journal
Silicon Demonstration of Hardware Trojan Design and Detection in Wireless Cryptographic ICs
IEEE Transactions on Very Large Scale Integration (T.VLSI)
·
2017
Conference
ACE: Adaptive Channel Estimation for Detecting Analog/RF Trojans in WLAN Transceivers
Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD)
·
2017
Conference
Automated Die Inking: A Pattern Recognition-Based Approach
Proceedings of the IEEE International Test Conference (ITC)
·
2017
Conference
Enhanced Hotspot Detection Through Synthetic Hotspot Generation and Design of Experiments
Proceedings of the SRC Technology and Talent for the 21st Century Conference (TECHCON)
·
2017
Best-in-Session Award
Conference
Wafer-Level Adaptive Trim Seed Forecasting
Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)
·
2017
Conference
Security and Trust in the Analog/Mixed-Signal/RF Domain: A Survey and a Perspective
Proceedings of the IEEE European Test Symposium (ETS)
·
2017
Conference
What to Lock? Functional and Parametric Locking
Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)
·
2017
Conference
INFECT: INconspicuous FEC-based Trojan: A Hardware Attack on an 802.11a/g Wireless Network
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST)
·
2017
Conference
Knob Non-Idealities in Learning-Based Post-Production Tuning of Analog/RF ICs: Impact & Remedies
Proceedings of the IEEE VLSI Test Symposium (VTS)
·
2017
Conference
Hardware-based On-line Intrusion Detection via System Call Routine Fingerprinting
Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE)
·
2017
Conference
Information Flow Tracking in Analog/Mixed-Signal Designs through Proof-Carrying Hardware IP
Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE)
·
2017
Conference
A Field Programmable Transistor Array Featuring Single-Cycle Partial/Full Dynamic Reconfiguration
Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE)
·
2017
Book chapter
Hardware Trojans in Analog, Mixed-Signal and RF ICs
In S. Bhunia and M. Tehranipoor (Editors), The Hardware Trojan War: Attacks, Myths, and Defenses, Springer
·
2017
2016
Journal
Toward Silicon-Based Cognitive Neuromorphic ICs - A Survey
IEEE Design & Test of Computers (D&T)
·
2016
Conference
Hardware-based Workload Forensics and Malware Detection in Microprocessors
Proceeding of the iEEE International Workshop on Microprocessor/SoC Test and Verification (MTV)
·
2016
Conference
A Machine Learning Approach to Fab-of-Origin Attestation
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
·
2016
Conference
Harnessing Process Variations for Optimizing Wafer-Level Probe-Test Flow
Proceedings of the IEEE International Test Conference (ITC)
·
2016
Conference
Hardware-Based Attacks to Compromise the Cryptographic Security of an Election System
Proceedings of the IEEE International Conference on Computer Design (ICCD)
·
2016
Conference
Harnessing Process Variation Signature for Dynamic Selection of Probe-Test Flow
Proceedings of the SRC Technology and Talent for the 21st Century Conference (TECHCON)
·
2016
Conference
-197dBc/Hz FOM 4.3-GHz VCO Using an Addressable Array of Minimum-Sized NMOS Cross-Coupled Transistor Pairs in 65-nm CMOS
Proceedings of the IEEE Symposium on VLSI Circuits (VLSI-Circuits)
·
2016
Conference
Harnessing Fabrication Process Signature for Predicting Yield Across Designs
Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)
·
2016
Conference
Hardware-Based Workload Forensics: Process Reconstruction via TLB Monitoring
Proceedings of the IEEE Symposium on Hardware-Oriented Security and Trust (HOST), pp. 167-172
·
2016
Conference
Wafer-Level Process Variation-Driven Probe-Test Flow Selection for Test Cost Reduction in Analog/RF ICs
Proceedings of the IEEE VLSI Test Symposium (VTS)
·
2016
Best Paper Award Candidate
Conference
On-Die Learning-Based Self-Calibration of Analog/RF ICs
Proceedings of the IEEE VLSI Test Symposium (VTS)
·
2016
2015
Journal
Multiple-Bit Upset Protection in Microprocessor Memory Arrays using Vulnerability-based Parity Optimization and Interleaving
IEEE Transactions on Very Large Scale of Integration Systems (T.VLSI)
·
2015
Journal
Revisiting Vulnerability Analysis in Modern Microprocessors
IEEE Transactions on Computers (TCOMP)
·
2015
Journal
An Experimentation Platform for On-chip Integration of Analog Neural Networks: A Pathway to Trusted and Robust Analog/RF ICs
IEEE Transactions on Neural Networks and Learning Systems (T.NNLS)
·
2015
Journal
Recycled IC Detection based on Statistical Methods
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T. CAD)
·
2015
Journal
Low-Cost Analog/RF IC Testing through Combined Intra- and Inter-Die Correlation Models
Special Issue on Speeding up Analog Integration and Test for Mixed-signal SOCs of the IEEE Design & Test of Computers (D&T)
·
2015
Conference
Yield Forecasting in Fab-to-Fab Production Migration Based on Bayesian Model Fusion
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD)
·
2015
Conference
A Comparative Study of One-Shot Statistical Calibration Methods for Analog / RF ICs
Proceedings of the IEEE International Test Conference (ITC)
·
2015
Conference
Concurrent Hardware Trojan Detection in Wireless Cryptographic ICs
Proceedings of the IEEE International Test Conference (ITC)
·
2015
Conference
Reliability Enhancement of Multi-core Processors Using Machine-Learning Techniques
Proceedings of the SRC Technology and Talent for the 21st Century Conference (TECHCON)
·
2015
Conference
Silicon Demonstration of Statistical Post-Production Tuning
Proceedings of the International Symposium on VLSI (ISVLSI)
·
2015
Conference
Workload Characterization and Prediction: A Pathway to Reliable Multi-core Systems
Proceedings of the International On-Line Test Symposium (IOLTS)
·
2015
Conference
Toward Automatic Proof Generation for Information Flow Policies in Third-Party Hardware IP
Proceedings of the IEEE Symposium on Hardware-Oriented Security and Trust (HOST)
·
2015
Conference
VeriCoq: a Verilog-to-Coq Converter for Proof-Carrying Hardware Automation
Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)
·
2015
Conference
Yield Prognosis for Fab-to-Fab Product Migration
Proceedings of the IEEE VLSI Test Symposium (VTS)
·
2015
Best Paper Award
Book chapter
Hardware Trojan Detection in Analog/RF Integrated Circuits
In C. H. Chang, M. Potkonjak (Editors), Secure System Design and Trustable Computing, Springer
·
2015
Book chapter
Machine Learning-Based BIST in Analog/RF ICs
In T. Noulis, M. Soma (Editors), Mixed-Signal Circuits, CRC Press
·
2015
2014
Journal
Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain
Proceedings of the IEEE (P.IEEE)
·
2014
Conference
Spatiotemporal Wafer-level Correlation Modeling with Progressive Sampling: A Pathway to HVM Yield Estimation
Proceedings of the IEEE International Test Conference (ITC)
·
2014
Conference
IC Laser Trimming Speed-Up through Wafer-level Spatial Correlation Modeling
Proceedings of the IEEE International Test Conference (ITC)
·
2014
Conference
On-chip intelligence: A pathway to self-testable, tunable, and trusted analog/RF ICs
Proceedings of IEEE Midwest Symposium on Circuits and Systems (MWSCAS)
·
2014
Conference
Hardware Trojan detection through golden chip-free statistical side-channel fingerprinting
Proceedings of the ACM/IEEE Design Automation Conference (DAC)
·
2014
Conference
An Analog Non-Volatile Neural Network Platform for Prototyping RF BIST Solutions
Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE)
·
2014
2013
Journal
On the Impact of Performance Faults in Modern Microprocessors
Journal of Electronic Testing: Theory & Applications (JETTA), Springer
·
2013
Journal
Low-cost Concurrent Error Detection for Floating Point Unit (FPU) Controllers
IEEE Transactions on Computers (TCOMP)
·
2013
Conference
A Proof-Carrying Based Framework for Trusted Microprocessor IP
Proceedings of the ACM/IEEE Design Automation Conference (ICCAD)
·
2013
Conference
Hardware Trojans in Wireless Cryptographic ICs: Silicon Demonstration & Detection Method Evaluation
Proceedings of the ACM/IEEE International Conference on Computer-Aided Design (ICCAD)
·
2013
Conference
Process Monitoring through Wafer-level Spatial Variation Decomposition
Proceedings of the IEEE International Test Conference (ITC)
·
2013
Conference
Counterfeit Electronics: A Rising Threat in the Semiconductor Manufacturing Industry
Proceedings of the IEEE International Test Conference (ITC)
·
2013
Conference
A Post-Deployment IC Trust Evaluation Architecture
Proceedings of the IEEE On-Line Test Symposium (IOLTS)
·
2013
Conference
Challenges and Benefits of Multiple Bit Upset (MBU) Vulnerability Analysis in Modern Microprocessors
Proceedings of the IEEE On-Line Test Symposium (IOLTS)
·
2013
Conference
Cycle Accurate Information Assurance by Proof Carrying-Based Signal Sensitivity Tracing
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST)
·
2013
Conference
Reconciling the IC Test and Security Dichotomy
Proceedings of the IEEE European Test Symposium (ETS)
·
2013
Conference
On Combining Alternate Test with Spatial Correlation Modeling in Analog/RF ICs
Proceedings of the IEEE European Test Symposium (ETS)
·
2013
Conference
Handling Discontinuous Effects in Modeling Spatial Correlation of Wafer-level Analog/RF Tests
Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE)
·
2013
Best Paper Award
Conference
AVF-driven Parity Optimization for MBU Protection of In-core Memory Arrays
Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE)
·
2013
Workshop
Analog Implementation of Ontogenic Neural Networks for RF Built-In Self-Test
Presented at the IEEE Test and Validation of High-Speed Analog Circuits
·
2013
2012
Journal
Global Signal Vulnerability (GSV) Analysis for Selective State Element Hardening on Modern Microprocessors
IEEE Transactions on Computers (TCOMP)
·
2012
Journal
Applying the Model-View-Controller Paradigm to Adaptive Test
Special Issue on Yield Learning of the IEEE Design and Test of Computers (D&T)
·
2012
Journal
Proof-Carrying Hardware Intellectual Property: A Pathway to Trusted Module Acquisition
Special Issue on Integrated Circuits and System Security of the IEEE Transactions on Information Forensics and Security (TIFS)
·
2012
Conference
Integrated Optimization of Semiconductor Manufacturing: A Machine Learning Approach
Proceedings of the IEEE International Test Conference (ITC)
·
2012
Conference
Spatial Estimation of Wafer Measurement Parameters Using Gaussian Process Models
Proceedings of the IEEE International Test Conference (ITC)
·
2012
Conference
Vulnerability-Based Interleaving for Multi-Bit Upset (MBU) Protection in Modern Microprocessors
Proceedings of the IEEE International Test Conference (ITC)
·
2012
Conference
Spatial Correlation Modeling For Probe Test Cost Reduction in RF Devices
Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD)
·
2012
Conference
Parametric Counterfeit IC Detection via Support Vector Machines
Proceedings of the IEEE Defect and Fault Tolerance Symposium (DFTS)
·
2012
Conference
Exposing Vulnerabilities of Untrusted Computing Platforms
Proceedings of the IEEE International Conference on Computer Design (ICCD)
·
2012
Conference
A Reconfigurable Dual-Mode Weight Storage Analog Neural Network Experimentation Platform
Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)
·
2012
Conference
Proof Carrying-Based Information Flow Tracking for Data Secrecy Protection and Hardware Trust
Proceedings of the IEEE VLSI Test Symposium (VTS)
·
2012
Conference
Post-Deployment Trust Evaluation in Wireless Cryptographic ICs
Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE)
·
2012
Book chapter
Checkers for On-line Self-Testing of Analog Circuits
In K. Iniewski (Editor), Advanced Circuits for Emerging Technologies, John Wiley & Sons
·
2012
2011
Journal
Improving Analog and RF Device Yield through Performance Calibration
IEEE Design and Test of Computers (D&T)
·
2011
Journal
A Workload-Cognizant Concurrent Error Detection Method for a Modern Microprocessor Controller
Special issue of IEEE Transactions on Computers (TCOMP) on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems
·
2011
Journal
Instruction-Level Impact Analysis of Low-Level Errors in a Modern Microprocessor Controller
Special issue of IEEE Transactions on Computers (TCOMP) on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems
·
2011
Conference
PSCML: Pseudo-Static Current Mode Logic
Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)
·
2011
Conference
On Proving the Performance of Alternative RF Tests
Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD)
·
2011
Conference
Is Single-Scheme Trojan Prevention Sufficient?
Proceedings of the IEEE International Conference on Computer Design (ICCD)
·
2011
Conference
Feature Selection Methods For Analog and RF Test: A Case Study
Proceedings of the SRC Technology and Talent for the 21st Century Conference (TECHCON)
·
2011
Best-in-Session Award
Conference
Enhancing Security via Provably Trustworthy Hardware Intellectual Property
Proceedings of the IEEE Symposium on Hardware-Oriented Security and Trust (HOST)
·
2011
Conference
AVF Analysis Acceleration via Hierarchical SFI
Proceedings of the IEEE European Test Symposium (ETS)
·
2011
Conference
PPM-Accuracy Error Estimates for Low-Cost Analog Test: A Case Study
Proceedings of the IEEE International Mixed Signals, Sensors, and Systems Workshop (IMS3TW)
·
2011
Best Student Paper Award
Conference
Exponent Monitoring for Low-Cost Concurrent Error Detection in FPU Control Logic
Proceedings of the IEEE VLSI Test Symposium (VTS)
·
2011
Conference
Correlating Inline Data with Final Test Outcomes in Analog/RF Devices
Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE)
·
2011
Book chapter
Design for Hardware Trust
In M. Tehranipoor, C. Wang (Editors), Introduction to Hardware Security and Trust, Springer
·
2011
2010
Journal
Hardware Trojans in Wireless Cryptographic Integrated Circuits
Special issue of IEEE Design & Test of Computers (D&T) on Verifying Physical Trustworthiness of Integrated Circuits and Systems
·
2010
Journal
RF Specification Test Compaction using Learning Machines
IEEE Transactions on Very Large Scale Integration (T.VLSI)
·
2010
Conference
DFTT: Design for Trojan Test
Proceedings of the IEEE International Conference on Electronics Circuits and Systems (ICECS)
·
2010
Conference
Analog Neural Network Design for RF Built-In Self-Test
Proceedings of the IEEE International Test Conference (ITC)
·
2010
Conference
Post-Production Performance Calibration in Analog/RF Devices
Proceedings of the IEEE International Test Conference (ITC)
·
2010
Conference
An Analog VLSI Implementation of a Multilayer Perceptron and its Application Towards Built-In Self-Test in Analog Circuits
Proceedings of the IEEE International On-Line Test Symposium (IOLTS)
·
2010
Conference
Workload-Driven Selective Hardening of Control State Elements in Modern Microprocessors
Proceedings of the IEEE VLSI Test Symposium (VTS)
·
2010
2009
Journal
On Boosting the Accuracy of Non-RF to RF Correlation-Based Specification Test Compaction
Journal of Electronic Testing Theory and Applications (JETTA)
·
2009
Journal
Parity-Based Concurrent Error Detection with Bounded-Latency in Finite State Machines
Kuwait Journal of Science and Engineering (KJSE)
·
2009
Journal
Soft Error Tolerance and Mitigation in Asynchronous Burst Mode Circuits
IEEE Transactions on Very Large Scale Integration (T.VLSI)
·
2009
Journal
Enhancing Simulation Accuracy through Advanced Hazard Detection in Asynchronous Circuits
IEEE Transactions on Computers (T.COMP)
·
2009
Conference
Impact Analysis of Performance Faults in Modern Microprocessors
Proceedings of the IEEE International Conference on Computer Design (ICCD)
·
2009
Conference
Post-Production Tuning in Analog and RF Devices
Proceedings of the SRC Technology and Talent for the 21st Century Conference (TECHCON)
·
2009
Conference
Experiences in Hardware Trojan Design and Implementation
Proceedings of the IEEE International Workshop on Hardware Oriented Security and Trust (HOST)
·
2009
Conference
Instruction-Level Impact Comparison of RT- vs. Gate-Level Faults in a Modern Microprocessor Controller
Proceedings of the IEEE VLSI Test Symposium (VTS)
·
2009
Conference
Enrichment of Limited Training Sets in Machine Learning-Based Analog/RF Test
Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE)
·
2009
2008
Journal
Error Moderation in Low-Cost Machine Learning-Based Analog/RF Testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T. CAD)
·
2008
Journal
A Novel Soft Error Rate (SER) Reduction Methodology through Addition of Gate-Level Functional Redundancy
IEEE Transactions on Reliability (T. REL)
·
2008
Conference
On the Correlation between Controller Faults and Instruction-Level Errors in a Modern Microprocessor
Proceedings of the IEEE International Test Conference (ITC)
·
2008
Conference
Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor Controller
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS)
·
2008
Conference
On the Minimization of Potential Transient Errors and SER in Logic Circuits using SPFD
Proceedings of the IEEE International On-Line Testing Symposium (IOLTS)
·
2008
Conference
Hardware Trojan Detection using Path Delay Fingerprint
Proceedings of the IEEE International Workshop on Hardware Oriented Security and Trust (HOST)
·
2008
Conference
Confidence Estimation in Non-RF to RF Correlation-Based Specification Test Compaction
Proceedings of the IEEE European Test Symposium (ETS)
·
2008
Conference
A Statistical Approach to Characterizing and Testing Functionalized Nanowires
Proceedings of the IEEE VLSI Test Symposium (VTS)
·
2008
Conference
Coping with Soft Errors in Asynchronous Burst-Mode Machines
Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
·
2008
2007
Journal
Concurrent Error Detection Methods for Asynchronous Burst Mode Machines
IEEE Transactions on Computers (T. COMP)
·
2007
Journal
On the Identification of Modular Test Requirements for Low-Cost Hierarchical Test Path Construction
Integration: The VLSI Journal (JVLSI)
·
2007
Conference
Non-RF to RF Test Correlation Using Learning Machines: A Case Study
Proceedings of the IEEE VLSI Test Symposium (VTS)
·
2007
Book chapter
Circuit-Level Approaches to Soft Error Mitigation
In L. T. Wang, C. E. Stroud, and N. A. Touba (Editors), System on-Chip Test Architectures, Morgan-Kaufman Publishers
·
2007
2006
Journal
An Adaptive Checker for the Fully Differential Analog Code
IEEE Journal of Solid-State Circuits (JSSC)
·
2006
Journal
Entropy-Driven Parity Tree Selection for Low-Cost Concurrent Error Detection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T. CAD)
·
2006
Journal
Concurrent Error Detection in Linear Analog Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T. CAD)
·
2006
Conference
Testing Delay Faults in Asynchronous Handshake Circuits
Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD)
·
2006
Conference
Seamless Integration of SER in Rewiring-Based Design Space Exploration
Proceedings of the IEEE International Test Conference (ITC)
·
2006
Conference
Bridging the Accuracy of Functional and Machine-Learning-Based Mixed-Signal Testing
Proceedings of the IEEE VLSI Test Symposium (VTS)
·
2006
Conference
A Transistor-Level Test Strategy for C2MOS MOUSETRAP Asynchronous Pipelines
Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
·
2006
Conference
Low-Overhead Testing of Delay Faults in High-Speed Asynchronous Pipelines
Proceedings of the IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
·
2006
Conference
Berger-Code-Based Concurrent Error Detection in Asynchronous Burst-Mode Machines
Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE)
·
2006
2005
Journal
Non-Linear Decision Boundaries for Testing Analog Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (T. CAD)
·
2005
Journal
Compaction-Based Concurrent Error Detection for Digital Circuits
Microelectronics Journal (MJ)
·
2005
Conference
Test Generation for Ultra-High-Speed Asynchronous Pipelines
Proceedings of the IEEE International Test Conference (ITC)
·
2005
Conference
Constructive Derivation of Analog Specification Test Criteria
Proceedings of the IEEE VLSI Test Symposium (VTS)
·
2005
Conference
Generating Decision Regions in Analog Measurement Spaces
Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)
·
2005
Conference
Concurrent Error Detection in Asynchronous Burst-Mode Controllers
Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE)
·
2005
Conference
SPIN-PAC: Test Compaction for Speed-Independent Circuits
Proceedings of the IEEE Asian South Pacific Design Automation Conference (ASP-DAC)
·
2005
2004
Journal
An Analog Checker with Input-Relative Tolerance for Duplicate Signals
Journal of Electronic Testing: Theory & Applications (JETTA)
·
2004
Journal
Enhancing Reliability of RTL Controller-Datapath Circuits via Invariant-Based Concurrent Test
IEEE Transactions on Reliability (T. REL)
·
2004
Conference
SPIN-TEST: Automatic Test Pattern Generation for Speed-Independent Circuits
Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD)
·
2004
Conference
SPIN-SIM: Logic and Fault Simulation for Speed-Independent Circuits
Proceedings of the IEEE International Test Conference (ITC)
·
2004
Conference
Compiler-Based Frame Formation for Static Optimization
Proceedings of the IEEE International Conference on Computer Design (ICCD)
·
2004
Conference
Fault Simulation and Random Test Generation for Speed Independent Circuits
Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)
·
2004
Conference
Cost-Driven Selection of Parity Trees
Proceedings of the IEEE VLSI Test Symposium (VTS)
·
2004
Conference
Concurrent Error Detection for Combinational and Sequential Logic via Output Compaction
Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)
·
2004
Conference
On Concurrent Error Detection with Bounded Latency in FSMs
Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE)
·
2004
Workshop
Roving Concurrent Error Detection for Logic Circuits
Presented at the IEEE North Atlantic Test Workshop
·
2004
2003
Journal
SPaRe: Selective Partial Replication for Concurrent Fault Detection in FSMs
IEEE Transactions on Instrumentation and Measurement (T. I &M)
·
2003
Conference
Low-Cost Convolutional Code Based Concurrent Error Detection in FSMs
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS)
·
2003
Conference
Fault Tolerant Design of Combinational and Sequential Logic based on a Parity Check Code
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS)
·
2003
Conference
Cost-Effective Graceful Degradation in Speculative Processor Subsystems: The Branch Prediction Case
Proceedings of the IEEE International Conference on Computer Design (ICCD)
·
2003
Conference
Independent Test Sequence Compaction through Integer Programming
Proceedings of the IEEE International Conference on Computer Design (ICCD)
·
2003
Conference
Concurrent Error Detection in Linear Analog Circuits Using State Estimation
Proceedings of the IEEE International Test Conference (ITC)
·
2003
Conference
An Analog Checker with Input-Relative Tolerance for Duplicate Signals
Proceedings of the IEEE On-Line Testing Symposium (IOLTS)
·
2003
Conference
On Compaction-Based Concurrent Error Detection
Proceedings of the IEEE On-Line Testing Symposium (IOLTS)
·
2003
Conference
An Analog Checker with Dynamically Adjustable Error Threshold for Fully Differential Circuits
Proceedings of the IEEE VLSI Test Symposium (VTS)
·
2003
Conference
Concurrent Fault Detection in Random Combinational Logic
Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)
·
2003
Conference
Non-Intrusive Concurrent Error Detection in FSMs through State/Output Compaction and Monitoring via Parity Trees
Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE)
·
2003
Conference
SPaRe: Selective Partial Replication for Concurrent Fault Detection in FSMs
Proceedings of the IEEE International Conference on VLSI Design (VLSI)
·
2003
Workshop
Fault Tolerant Design of Random Logic based on a Parity Check Code
Presented at the IEEE European Test Workshop
·
2003
Workshop
On the Compaction of Independent Test Sequences for Sequential Circuits
Presented at the IEEE European Test Workshop, Maastricht
·
2003
2002
Journal
Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface
Journal of Electronic Testing: Theory & Applications (JETTA)
·
2002
Conference
Non-Intrusive Design of Concurrently Self-Testable FSMs
Proceedings of the IEEE Asian Test Symposium (ATS)
·
2002
Conference
Test Requirement Analysis for Low Cost Hierarchical Test Path Construction
Proceedings of the IEEE Asian Test Symposium (ATS)
·
2002
Conference
Duplication-Based Concurrent Error Detection in Asynchronous Circuits: Shortcomings and Remedies
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS)
·
2002
Workshop
Reducing Hierarchical Test Path Cost via Modular Test Requirement Analysis
Presented at the IEEE European Test Workshop
·
2002
Workshop
Non-Intrusive Design of Concurrently Self-Testable FSMs
Presented at the IEEE North Atlantic Test Workshop
·
2002
2001
Conference
Efficient Transparency Extraction and Utilization in Hierarchical Test
Proceedings of the IEEE VLSI Test Symposium (VTS)
·
2001
Workshop
Test Requirement Analysis for Low Cost Hierarchical Test Path Construction
Presented at the IEEE International Workshop of RTL Test Generation
·
2001
2000
Conference
Fast Hierarchical Test Path Construction for Controller-Datapath Circuits without DFT
Proceedings of the IEEE Asian Test Symposium (ATS)
·
2000
Conference
How to Avoid Random Walks in Hierarchical Test Path Identification
Formal Proceedings of the IEEE European Test Workshop (ETW)
·
2000
Conference
Modular Test Generation and Concurrent Transparency-Based Test Translation Using Gate-Level ATPG
Proceedings of the IEEE Custom Integrated Circuits Conference (CICC)
·
2000
Conference
Transparency-Based Hierarchical Test Generation for Modular RTL Designs
Proceedings of the IEEE International Symposium of Circuits and Systems (ISCAS)
·
2000
Conference
Invariance-Based On-Line Test for RTL Controller-Datapath Circuits
Proceedings of the IEEE VLSI Test Symposium (VTS)
·
2000
Workshop
How to Avoid Random Walks in Hierarchical Test Path Identification
Presented at the IEEE European Test Workshop
·
2000
Workshop
Exploiting Off-Line Hierarchical Test Paths in Module Diagnosis and On-Line Test
Presented at the IEEE Latin American Test Workshop
·
2000
1999
Journal
RTL Test Justification and Propagation Analysis for Modular Designs
Journal of Electronic Testing: Theory & Applications (JETTA)
·
1999
Conference
A Module Diagnosis and Design-for-Debug Methodology based on Hierarchical Test Paths
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS)
·
1999
Conference
Property-Based Testability Analysis for Hierarchical RTL Designs
Proceedings of the IEEE International Conference on Electronics Circuits and Systems (ICECS)
·
1999
Conference
TRANSPARENT: A System for RTL Testability Analysis, DFT Guidance and Hierarchical Test Generation
Proceedings of the IEEE Custom Integrated Circuits Conference (CICC)
·
1999
Conference
Channel-Based Behavioral Test Synthesis for Improved Module Reachability
Proceedings of the IEEE Design Automation and Test in Europe Conference (DATE)
·
1999
1998
Conference
DFT Guidance Through RTL Test Justification and Propagation Analysis
Proceedings of the IEEE International Test Conference (ITC)
·
1998
Workshop
Property-Based RTL Test Justification and Propagation Analysis
Presented at the IEEE International Test Synthesis Workshop
·
1998