Yiorgos Makris directs the Trusted and RELiable Architectures (TRELA) Lab. His research applies machine learning and statistical analysis to the design of trusted and reliable integrated circuits and systems, with particular emphasis on the analog/RF domain. He also works on hardware-based malware detection, forensics and reliability in modern microprocessors, security primitives in synthetic biology, on-die learning, and novel computational modalities built on emerging technologies.
Before moving to UC San Diego, he was a Professor of Electrical and Computer Engineering at The University of Texas at Dallas, which he joined in 2011, and before that spent 10.5 years on the faculty of Electrical Engineering and Computer Science at Yale University. He holds a Ph.D. (2001) and an M.S. (1997) in Computer Engineering from UC San Diego and a Diploma (1995) in Computer Engineering and Informatics from the University of Patras, Greece. He co-founded the NSF Industry-University Cooperative Research Center on Hardware and Embedded System Security and Trust (CHEST) and led the Safety, Security and Healthcare thrust of the Texas Analog Center of Excellence (TxACE).
His research has been supported by NSF, NIH, SRC, ARO, AFRL, AFWERX, DARPA, DoE/Honeywell, Boeing, Northrop Grumman, KBR/Wyle, IBM, LSI, Intel, AMS, Advantest, NXP, Qualcomm and TI.
Honors
- IEEE Fellow, Class of 2025
- Erik Jonsson School Faculty Research Award, UT Dallas (2020)
- Best Paper Awards: DATE 2013, VTS 2015, and IEEE DCAS 2022
- Best Hardware Demonstration Awards: IEEE HOST 2016 and HOST 2018
- IEEE Hardware Security Top Picks: TCAD 2015 (statistical recycled IC detection) and DAC 2015 (golden-chip-free hardware Trojan detection)
- Sheffield Distinguished Teaching Award, Yale University (2006)
Professional service
- General Chair, IEEE VLSI Test Symposium (VTS 2016 and 2017) and TxACE Workshop on Secure and Trusted Analog/RF Systems (STARS 2018)
- Program Chair, IEEE VLSI Test Symposium (VTS 2013 and 2014), TxACE Symposium (2015, 2022, 2025), and IEEE TTTC Test Technology Education Program (2010 to 2012)
- Associate Editor, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2018 to 2021), IEEE Transactions on Information Forensics and Security (2015 to 2018), IEEE Design & Test (2015 to 2018), and Springer JETTA (2015 to 2018)
- Guest Editor, IEEE TCAD Special Section on Hardware Security and Trust (2015) and IEEE Transactions on Computers Special Section on Chips and Architectures for Emerging Technologies (2011)
Selected invited talks
- “Provenance Attestation: From Silicon Chips to Biological Cells and Beyond”, Sorbonne University (2025), Texas A&M (2025), Colorado School of Mines (2025), Purdue (2024), UC San Diego (2023), USC (2023)
- “Malicious Hardware-Induced Covert Channels in Wireless Networks: Risks and Remedies”, University of Maryland (2022) and University of Athens (2022)
- “Applications of Machine Learning in Hardware Security”, keynote at IEEE DCAS (2022)
- “Machine Learning in Semiconductor Manufacturing and Test: Fallacies, Pitfalls and Marching Orders”, keynotes at Si2 AI/ML Workshop (2021) and IEEE DDECS (2021)
Teaching
- Computer Architecture (undergraduate and graduate)
- Trusted and Secure Integrated Circuits and Systems
- Applications of Machine Learning in Semiconductor Manufacturing
- Digital System Test and Design for Testability
- Introduction to Electrical and Computer Engineering